practice5

module top;
wire x_in1,x_in2,x_in3,x_in4;
wire y_out;
system_clock #100 clock1(x_in1);
system_clock #200 clock2(x_in2);
system_clock #400 clock3(x_in3);
system_clock #800 clock4(x_in4);
test AH1(y_out,x_in1,x_in2,x_in3,x_in4);

endmodule

module test(y_out,x_in1,x_in2,x_in3,x_in4);

input x_in1,x_in2,x_in3,x_in4;
output y_out;
wire y1,y2;

and #1(y1,x_in1,x_in2);
and #1(y2,x_in3,x_in4);
nor #1(y_out,y1,y2);
endmodule

module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial
clk = 0;
always
begin
#(PERIOD/4) clk = ~clk;
#(PERIOD/4) clk = ~clk;
#(PERIOD/4) clk = ~clk;
#(PERIOD/4) clk = ~clk;
end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule