課堂練習2

題目:Design a verilog model of a adder and write a testbench to verify the designed verilog model


p.q:
module add_half(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;
xor(sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule