1位元全加法器

module top;
wire a,b,c_in;
wire sum,c_out;
system_clock #100 clock1(a);
system_clock #200 clock2(b);
system_clock #400 clock3(c_in);
test AH1(sum,c_out,a,b,c_in);

endmodule

module add_half(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;
xor(sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule

module test(sum,c_out,a,b,c_in);
input a,b,c_in;
output sum,c_out;
wire w1,w2,w3;
add_half M1(w1,w2,a,b);
add_half M2(sum,w3,w1,c_in);
or (c_out,w2,w3);
endmodule

module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial
clk = 0;
always
begin
#(PERIOD/3) clk = ~clk;
#(PERIOD/3) clk = ~clk;
#(PERIOD/3) clk = ~clk;

end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule

practice5

module top;
wire x_in1,x_in2,x_in3,x_in4;
wire y_out;
system_clock #100 clock1(x_in1);
system_clock #200 clock2(x_in2);
system_clock #400 clock3(x_in3);
system_clock #800 clock4(x_in4);
test AH1(y_out,x_in1,x_in2,x_in3,x_in4);

endmodule

module test(y_out,x_in1,x_in2,x_in3,x_in4);

input x_in1,x_in2,x_in3,x_in4;
output y_out;
wire y1,y2;

and #1(y1,x_in1,x_in2);
and #1(y2,x_in3,x_in4);
nor #1(y_out,y1,y2);
endmodule

module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial
clk = 0;
always
begin
#(PERIOD/4) clk = ~clk;
#(PERIOD/4) clk = ~clk;
#(PERIOD/4) clk = ~clk;
#(PERIOD/4) clk = ~clk;
end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule

PRACTICE4-全加法器

module Add_full(sum,c_out,a,b,c_in);

input a,b,c_in;
output sum_c_out;
wire w1,w2,w3;

Add_half M1(w1,w2,a,b);
Add_half M2(sum,w3,w1,c_in);
or (c_out,w2,w3);

endmodule;

練習3-半加法器

module top;
wire a,b;
wire sum,c_out;

system_clock #100 clock1(a);
system_clock #50 clock2(b);

Add_half AH1(sum,c_out,a,b);

endmodule

module Add_half(sum,c_out, a, b);

input a,b;
output sum,c_out;
wire c_out_bar;


xor(sum, a, b);
nand(c_out_bar, a, b);
not(c_out,c_out_bar);
endmodule


module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial
clk = 0;
always
begin
#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule

課堂練習2

題目:Design a verilog model of a adder and write a testbench to verify the designed verilog model


p.q:
module add_half(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;
xor(sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule

練習

上禮拜練習的作業
今天上課又練習了一次
發現寫程式真的要很細心
少一個分號都不行
或是任何一個大小寫沒有統一也會發生錯誤
所以
寫程式還真的需要更多的耐心和細心