
module top;
wire a,b,c,d,f;
system_clock #400 clock(a);
system_clock #200 clock(b);
system_clock #100 clock(c);
system_clock #50 clock(d);
unit u1(f,a,b,c,d);
endmodule
module unit(f,a,b,c,d);
input a,b,c,d;
output f;
wire w1,w2,w3;
wire a_bar,b_bar,c_bar,d_bar;
not (a_bar,a);
not (b_bar,b);
not (c_bar,c);
not (d_bar,d);
and (w1,a_bar,b_bar,d);
and (w2,b,d_bar);
and (w3,a,b_bar,c);
or (f,w1,w2,w3);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule
wire a,b,c,d,f;
system_clock #400 clock(a);
system_clock #200 clock(b);
system_clock #100 clock(c);
system_clock #50 clock(d);
unit u1(f,a,b,c,d);
endmodule
module unit(f,a,b,c,d);
input a,b,c,d;
output f;
wire w1,w2,w3;
wire a_bar,b_bar,c_bar,d_bar;
not (a_bar,a);
not (b_bar,b);
not (c_bar,c);
not (d_bar,d);
and (w1,a_bar,b_bar,d);
and (w2,b,d_bar);
and (w3,a,b_bar,c);
or (f,w1,w2,w3);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule