電路危障

If a circuit has a hazard it could exhibit a glitch certain conditions.

2位元比較器行為模式:

2位元比較器行為模式:

module compare_2_algo(A_lt_B,A_gt_B,A_eq_B);
input [1:0] A,B; //四位元則改成[3:0]
output
reg A_lt_B,A_gt_B,A_eq_B;
always@(A or B)
begin
A_lt_B=0;
A_gt_B=0;
A_eq_B=0;
if (A==B) A_eq_B=1;
else if (A>B) A_gt_B=1;
else A_lt_B=1;
end
endmodule

2位元比較器

module compare_2_str(A_lt_B,A_gt_b,A_eq_B,A0,A1,Bo,B1);
input A0,A1,B0,B1;
output A_lt_B,A_gt_B,A_eq_B;
wire w1,w2,w3,w4,w5,w6,w7;
or (A_lt_B.w1,w2,w3);
nor (A_gt_B,A_lt_B,A_eq_B);
and (A_eq_B,w4,w5);
and (w1,w6,B1);
and (w2,w6,w7,B0);
and (w3,w7,B0,B1);
not (w6,A1);
not (w7,A0);
xnor (w4,A1,B1);
xnor (w5,A0,B0);
endmodule




Verilog RTL model (Register Transfer Level):

module compare_2a(A_lt_B,A_gt_b,A_eq_B,A0,A1,Bo,B1);
input A0,A1,B0,B1;
output A_lt_B,A_gt_B,A_eq_B;
assign A_lt_B=(~A1)&B1(A1)&(~A0)&B0(~A0)&B1B0;

assign A_gt_B=A1&(B1)A0&(~B1)&(~B0)A1&A0&(~B0);
assign A_eq_B=......;
endmodule

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