vlog

module top;
wire a,b,c,d,f;
system_clock #400 clock(a);
system_clock #200 clock(b);
system_clock #100 clock(c);
system_clock #50 clock(d);
unit u1(f,a,b,c,d);
endmodule


module unit(f,a,b,c,d);
input a,b,c,d;
output f;
wire w1,w2,w3;
wire a_bar,b_bar,c_bar,d_bar;
not (a_bar,a);
not (b_bar,b);
not (c_bar,c);
not (d_bar,d);


and (w1,a_bar,b_bar,d);
and (w2,b,d_bar);
and (w3,a,b_bar,c);

or (f,w1,w2,w3);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

冷!

天氣好冷
沒長袖只有短袖能穿
冷死人

電路危障

If a circuit has a hazard it could exhibit a glitch certain conditions.

2位元比較器行為模式:

2位元比較器行為模式:

module compare_2_algo(A_lt_B,A_gt_B,A_eq_B);
input [1:0] A,B; //四位元則改成[3:0]
output
reg A_lt_B,A_gt_B,A_eq_B;
always@(A or B)
begin
A_lt_B=0;
A_gt_B=0;
A_eq_B=0;
if (A==B) A_eq_B=1;
else if (A>B) A_gt_B=1;
else A_lt_B=1;
end
endmodule

2位元比較器

module compare_2_str(A_lt_B,A_gt_b,A_eq_B,A0,A1,Bo,B1);
input A0,A1,B0,B1;
output A_lt_B,A_gt_B,A_eq_B;
wire w1,w2,w3,w4,w5,w6,w7;
or (A_lt_B.w1,w2,w3);
nor (A_gt_B,A_lt_B,A_eq_B);
and (A_eq_B,w4,w5);
and (w1,w6,B1);
and (w2,w6,w7,B0);
and (w3,w7,B0,B1);
not (w6,A1);
not (w7,A0);
xnor (w4,A1,B1);
xnor (w5,A0,B0);
endmodule




Verilog RTL model (Register Transfer Level):

module compare_2a(A_lt_B,A_gt_b,A_eq_B,A0,A1,Bo,B1);
input A0,A1,B0,B1;
output A_lt_B,A_gt_B,A_eq_B;
assign A_lt_B=(~A1)&B1(A1)&(~A0)&B0(~A0)&B1B0;

assign A_gt_B=A1&(B1)A0&(~B1)&(~B0)A1&A0&(~B0);
assign A_eq_B=......;
endmodule

陳珮容你有種!

每次都在期中期末的時候才要吵我!下禮拜換我去中壢找你玩!咱們不醉不歸阿!

1位元全加法器

module top;
wire a,b,c_in;
wire sum,c_out;
system_clock #100 clock1(a);
system_clock #200 clock2(b);
system_clock #400 clock3(c_in);
test AH1(sum,c_out,a,b,c_in);

endmodule

module add_half(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;
xor(sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule

module test(sum,c_out,a,b,c_in);
input a,b,c_in;
output sum,c_out;
wire w1,w2,w3;
add_half M1(w1,w2,a,b);
add_half M2(sum,w3,w1,c_in);
or (c_out,w2,w3);
endmodule

module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial
clk = 0;
always
begin
#(PERIOD/3) clk = ~clk;
#(PERIOD/3) clk = ~clk;
#(PERIOD/3) clk = ~clk;

end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule